1. Field of the Invention
The present invention generally relates to determining multi-patterning step overlay error. Certain embodiments relate to methods and systems for determining overlay error between different patterned features printed on a level of a wafer in different steps of a multi-patterning step process.
2. Description of the Related Art
The following description and examples are not admitted to be prior art by virtue of their inclusion in this section.
Fabricating semiconductor devices such as integrated circuits involves forming multiple layers on a wafer. Different structures are formed on different layers of the wafer, and some structures are intended to be electrically connected to each other while other structures are intended to be insulated from one another. If the structures on one layer are not properly aligned with other structures of the same or other layers, the misalignment of the structures can prevent the proper electrical connection of some structures and/or the proper insulation for other structures. Therefore, measuring and controlling the alignment of structures on a wafer is important in the successful manufacture of working semiconductor devices.
Generally, the alignment of structures on a wafer is determined by the error sources (e.g., alignment of a reticle, alignment of the wafer, etc.) in an exposure step of a lithography process performed on the wafer. In particular, since the lithography process involves forming patterned features in a resist material that are then transferred to a device material using other fabrication processes, the lithography process generally controls where the patterned features and therefore where device structures formed from the patterned features) are formed on the wafer. Therefore, measuring and controlling alignment of features on one layer with respect to features on the same or another layer before, during, and/or after the lithography process is a critical step in the fabrication process.
Accordingly, it would be advantageous to develop systems and methods for determining overlay error between different patterned features of a design printed on a wafer in a multi-patterning step process that do not have one or more of the disadvantages of currently used methods and systems.